(A) Field of the Invention
The present invention relates to a system and method for constructing variations from an integrated circuit layout, and more particularly, to a system and method for manipulating an integrated circuit layout allowing for reuse and migration.
(B) Description of the Related Art
Semiconductor circuits or chips have become widely used in articles for daily use. A typical electronic circuit design is initially conceived and tested schematically by a circuit design engineer; with a number of components and devices connected together to yield a circuit with desired performance characteristics. Once the circuit has been designed, it must be reconfigured from schematic form into a geometric layout form. This is typically a job for a physical design engineer, working in concert with the circuit design engineer to create a graphic layout specifying a suitable semiconductor implementation of the circuit. The geometric layout of the device, which specifies all of the semiconductor device layout parameters, is then submitted to a foundry for fabrication of the chip.
Configuring the geometric layout from the schematic form for an electronic circuit is a very complicated task, and is governed by a large number of geometric rules. A geometric layout of a semiconductor device contains geometric features such as polygons to indicate the proper size, shape, location and separation of a certain physical feature of the circuit, distinguishing it from other physical features, or to indicate proper isolation and separation among the circuit elements. The geometric layout of a typical semiconductor device contains multiple drawing layers, each layer having one or more polygons. Generally, the more complicated the device is, the more layers and polygons the layout includes.
In addition, to layout another semiconductor device, the circuit design engineer and the physical design engineer have to restart the complicated task. Even the circuit design of the semiconductor device is to be fabricated by a new fabrication process rather than a predetermined process; the circuit design engineer and the physical design engineer have to modify the parameters of the circuit layout to meet constraints of the new fabrication process, which is time-consuming and error prone. In other words, the prior art consumes a lot of effort for the existing layout to be reused or migrated to a different fabrication process.